This application relies for priority upon Korean Patent Application No. 2001-47944, filed on Aug. 9, 2001, the contents of which are herein incorporated by this reference in their entirety.
The present invention generally relates to a non-volatile semiconductor memory device and a method of forming the same. More specifically, the invention is directed to a semiconductor memory device having a floating trap-type memory cell and a method of forming the same.
A non-volatile memory device such as a flash memory device continuously holds data until it is erased. Therefore, unlike a volatile memory device such as a normal DRAM, the non-volatile memory device does not require refresh-related circuitry and can save power consumption.
However, the non-volatile memory device needs a high voltage for writing/erasing data and an extra storage for holding data. This complicates the structure and forming processes. For example, the non-volatile memory device may additionally need a charge storage for reliably preserving data and a voltage drop resistor for driving high and low voltage areas from a single power source.
Based upon a structure, memory cells of the non-volatile memory device type are classified into a floating gate type memory cell and a floating trap-type memory cell. In the floating trap-type memory cell, programming can be carried out by storing a charge in a trap formed in a non-conducive charge storage layer between a gate electrode and a semiconductor substrate. To form a floating trap, a tunneling insulating layer and a blocking insulating layer are formed on/beneath a silicon nitride layer acting as a charge storage layer.
FIG. 1 is a cross-sectional view showing a typical SONOS (silicon oxide nitride oxide semiconductor) structure of the floating trap-type memory device. A memory cell has a gate pattern and impurity diffusion layers. A gate pattern is formed by sequentially stacking a tunneling insulating layer 20, a charge storage layer 22, a blocking insulating layer 24, and a gate electrode 27 on an active region of a semiconductor substrate 10. An impurity diffusion layer 28 is formed in an active region on both sides of the gate pattern. Typically, the tunneling insulating layer 20 is made of thermal oxide and the charge storage layer 22 is made of silicon nitride.
In a non-volatile semiconductor memory device having a floating gate, a gate insulating layer of a memory cell conventionally has the same thickness as a gate insulating layer for forming a transistor of a low-voltage area in a peripheral circuit region. However, a tunneling insulating layer of the floating trap-type memory cell conventionally is different, in suitable thickness, from a gate insulating layer for forming a transistor of a lower voltage area in a peripheral circuit region. Therefore, the process for fabricating a non-volatile semiconductor device having the floating trap-type memory cell is more complex than the process for fabricating a non-volatile semiconductor device having the floating gate-type memory cell.
The present invention alleviates the complexity of the process for fabricating a non-volatile semiconductor memory device having a floating trap-type memory cell.
Therefore, the present invention provides a non-volatile semiconductor memory device having a floating trap-type memory cell that achieves process simplification and enhanced reliability, and a method of fabricating the same.
Furthermore, the present invention provides a non-volatile semiconductor memory device with improved efficiency in conveying a drive signal, and a method of fabricating the same.
According to one aspect of the present invention, a non-volatile semiconductor memory device comprises a cell gate pattern of a cell array region, a high-voltage-type gate pattern of a peripheral high-voltage region, and a low-voltage-type gate pattern of a peripheral low voltage region on a semiconductor substrate. The high-voltage type gate pattern has a gate insulating layer for a high voltage, a first conductive layer, a triple layer, and a second conductive layer. The cell gate pattern has only the triple layer and the second conductive layer. The triple layer includes a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. The low-voltage-type gate pattern has a gate insulating layer for a low voltage, the first conductive layer, the triple layer, and the second conductive layer.
The non-volatile memory device further comprises a line-type resistor pattern in a resist region. The resistor pattern has at least the first conductive layer formed on a gate insulating layer for electrical isolation from the substrate. The first conductive layer is made of doping-controlled polysilicon, acting as a resist layer. The insulating layer is a trench-type device isolation layer or an insulating layer for a high voltage. The resistor pattern has a contact region including the gate insulating layer for a high voltage and the first conductive layer and a line region including the gate insulating layer for a high voltage, the first conductive layer, the triple layer, and the second conductive layer. A contact formed over the resistor pattern is not electrically connected to the second conductive layer in the contact region. The cell gate pattern, the high-voltage-type gate pattern, and the low-voltage-type gate pattern have an insulating spacer on their sidewalls.
The second conductive layer is a dual layer comprising a lower layer of polysilicon and an upper layer of metal silicide.
A region of each of the gate pattern and the resistor pattern may have a contact for coupling to an upper circuit. That is, a contact plug may be made over a part of the pattern. When the second conductive layer and the triple layer are removed in a part of the contact region in the respective low-and high-voltage-type gate patterns, a butting contact is formed to concurrently connect to the first and second conductive layers in the contact region. If the second conductive layer and the triple layer are removed in at least the contact region of the resistor pattern and a contact plug is formed, only the first conductive layer of the line type resistor pattern is used as a resist layer.
Further, a top surface level of the triple layer is lower than a top surface level of a trench type device isolation layer formed at the substrate in the cell gate pattern. A bottom surface level of the triple layer is higher than a top surface level of the trench type device isolation layer in peripheral high-and low-voltage-type device regions. A top surface level of the lower conductive layer of the gate pattern is lower than a top surface level of the device isolation layer in a region where the gate pattern for a memory component, the high-voltage-type gate pattern, and the low-voltage-type gate pattern are formed.
According to another embodiment of the present invention, a non-volatile memory device is similar to the non-volatile memory device of the first embodiment. However, a triple layer is not formed and a simple contact is formed instead of a butting contact. More specifically, a high-voltage-type gate pattern has a gate insulating layer for a high voltage, a first conductive layer, and a high-conductivity layer. A cell gate pattern has a triple layer, a second conductive layer, and the high-conductivity layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. A low-voltage-type gate pattern has a gate insulating layer for a low voltage, the first conductive layer, and the high-conductivity layer. The high-conductivity layer is a metal-containing single layer or a dual layer include a lower layer of polysilicon and an upper layer of metal.
In this non-volatile semiconductor memory device, a line-type resistor pattern is formed. The resistor pattern of this embodiment is identical to that of the first embodiment. Each of the gate patterns and the resistor pattern may have a contact coupling to an upper circuit. However, in a layer structure of the resistor pattern, a contact forming region has a resist layer that is separated from the substrate by an insulating layer. The resistor layer is formed of a first conductive layer. If the high-conductivity layer is formed of a dual layer having a lower layer of polysilicon and an upper layer of metal silicide, the resistor layer may be formed of a combination layer of the first conductive layer and the polysilicon layer of the high-conductivity layer. The line region of the resistor pattern, except the contact region, has the same structure as the contact region or a structure where the triple layer, the second conductive layer, and the low resist conductive layer are sequentially stacked on the resist layer.
Further, a top surface level of the triple layer is lower than a top surface level of the trench type device isolation layer formed at the substrate in the cell array region. A top surface level of the first conductive layer is higher than a top surface level of the trench type device isolation layer in the peripheral high-and low-voltage type regions. In the cell array region, a top surface level of the trench type device isolation layer formed on the substrate is higher than a top surface level of the second conductive layer and is lower than a top surface level of the polysilicon layer of the high-conductivity layer. In the peripheral high-and low-voltage type regions, a top surface level of the trench-type device isolation layer is higher than a top surface level of the first conductive layer and is lower than a top surface level of the polysilicon layer of the high-conductivity layer.
In this embodiment, the tunneling insulating layer of the triple layer is conventionally made of thin silicon thermal oxide. The charge storage layer and the blocking insulating layer thereof are conventionally made of silicon nitride and silicon oxide respectively by a CVD technique. the gate patterns have an insulating spacer that is typically made of silicon nitride on their sidewall.
According to still another aspect of the present invention, a method of fabricating a non-volatile semiconductor memory device comprises forming a device isolation layer in a substrate, forming a low-voltage gate insulating layer in at least a peripheral low-voltage region of the substrate, and forming a high-voltage gate insulating layer in at least a peripheral high voltage region of the substrate, stacking a first conductive layer over substrate, performing a patterning process to remove the first conductive layer in a cell array region and to expose the substrate, and sequentially forming a triple layer and a second conductive layer over substantially the entire surface of the exposed substrate in the cell array region. The triple layer includes a tunneling insulating layer, a charge storage layer, and a blocking insulating layer.
In the cell array region, the tunneling insulating layer, the peripheral low-voltage gate insulating layer, and the peripheral high-voltage gate insulating layer may be differently formed. The structure of the gate pattern may be different from that of the peripheral high-and low-voltage-type gate patterns.
The present invention can be applied to cases wherein a device isolation layer is first formed as well as cases wherein one layer of the gate pattern is formed and then a trench-type device isolation layer is formed. Further, the present invention can be applied to cases wherein peripheral low-and high-voltage-type gate patterns having an insulating layer therein are formed over a butting contact, as well as cases wherein a simple contact connected to an uppermost layer is formed without the insulating layer. The present invention can be in cases wherein a resist layer of a resistor pattern is formed over a device isolation layer, as well as cases wherein the resist layer thereof is formed over an insulating layer such as a high-voltage gate insulating layer.